Introduction to VHDL

Front Cover
Springer Science & Business Media, 1996 - 482 pages
This book, based on extensive experience teaching VHDL to undergraduate students at the University of Portsmouth, UK, and to engineers in industry through short courses run by Mentor Graphics Corporation, USA, enables students and engineers to master VHDL. Introduction to VHDL covers all aspects of the VHDL language, including the latest information on the VHDL standard as of April 1995 and the fundamentals of design constructs and modelling.
 

Contents

Introduction
1
12 The means for change
4
13 Why use VHDL?
5
14 Summary of Chapters
6
References
8
Hardware Design Processes
9
21 Design Constructs
10
22 Design Levels
12
106 Fourtosixteen Decoder
237
107 ASSERT Statement
239
108 Severity Levels
241
109 Placing ASSERT Statements
243
1091 ASSERTed Decoder
245
1010 Exercises
246
Subprograms
247
111 Subprograms
249

23 Geometrybased Interchange Formats
17
24 Schematic Circuit Capture
19
26 Hardware Simulation
20
27 Hardware Synthesis
21
References
22
IEEE Standard VHDL Language
23
31 VHDL Reserved Words
24
32 VHDL Structure
25
33 A Design Example
28
Reference
34
Modelling with VHDL
35
41 Model Development
37
42 Specification
39
43 Analysis
41
45 Model Structure
43
451 entity Declaration
45
452 port Statement
47
453 port Mode
49
454 Architecture Body
51
455 Commenting Code
53
456 norgate Architecture Body
55
457 norgate Model
57
46 Exercises
58
Objects Data Types and Operators
59
51 Objects
61
511 Declaring Objects
63
512 Naming Objects
65
513 Signal Assignment
67
514 Conditional Signal Assignment
69
53 Data Types
71
531 Scalar Types
73
533 Predefined Types
75
534 NonSTANDARD Predefined Types
77
535 Accessing User Predefined Packages
79
54 Operators
81
541 Logical Operators
83
543 xorgate
85
55 Delay
87
551 Inertial Delay
89
553 A Delayed xorgate Model
91
554 Signal Duration
93
555 Transport Option
95
Reference
96
Multiple Architectures and Concurrency
97
61 Multiple Architectures
99
611 Multiple Architectures Example
101
62 Signal Drivers
103
621 Filling Drivers
105
63 Concurrency
107
631 Concurrent Execution
109
632 Concurrent Statements
111
64 Statement Activation
113
65 Defining Additional Signals
115
66 Concurrent Signal Change
117
68 Iterations
119
69 Exercises
122
Sequential Statements and Processes
123
71 Styles of Modelling
125
711 Algorithmic nandgate Model
127
72 process Statement
129
721 Labels
131
73 Sequential Operations
133
731 Sequential Statements
135
74 wait Statement
137
741 wait Control
139
742 Gated d_latch
141
75 process Sensitivity List
143
76 variable Definition
145
761 signal vs variable Assignment
147
77 Sequential Signal Assignment
149
78 Exercises
150
Sequential Modelling and Attributes
151
81 Sequential Modelling
153
82 Controlling Sequential Code
155
821 if Statement
157
83 Relational Operators
159
831 ifelse Construction
161
832 elsif Construction
163
84 Algorithmic nor_gate
165
85 Modelling Enables
167
86 Modelling Oscillators
169
87 Modelling Clocks
171
88 Modelling Synchronous Devices
173
89 Edge Triggering
175
810 Attributes
177
8101 Predefined Signal Attributes
179
8102 Checks with Attributes
181
811 Edgetriggered d_flip_flop
183
812 Checking Setup Time
185
8121 Checking Hold Time
187
813 Exercises
188
Conditional Assignments Concatenation and Case
189
91 Data Selection
191
92 Conditional Signal Assignment
193
921 Using Conditional Signal Assignment
195
922 Selected Signal Assignment
197
93 when Clause
199
931 others and unaffected
201
94 Concatenation
203
941 Typemarks
205
95 Sequential Selection
207
96 case Statement
209
97 null
211
98 Sequential one_of_four
213
99 An Exercise in Concatenation
215
910 Exercises
216
Arrays Loops and Assert Statements
217
101 Array Input one_bit_adder
219
102 Arrays
221
1021 Predefined Array Attributes
223
103 Loops
225
1031 for loop
227
1032 while loop
229
1033 loopexit Construct
231
104 exit Statement
233
105 next Statement
235
112 Functions
251
1121 function Declaration
253
1122 Parameter List
255
1123 return Type
257
1124 function Body
259
1125 return Statement
261
1126 transfer_check Function
263
1127 function Calls
265
1128 Passing Parameter List
267
113 bit_to_boolean
269
114 Procedures
271
1141 procedure Declaration
273
1142 Parameter List
275
1143 Parameter Modes
277
1144 procedure Body
279
1145 find_minimum procedure
281
1146 procedure Calls
283
1147 Passing Parameter List
285
115 Exercises
286
Types and Arithmetic Operations
287
121 Typing
289
1211 Integer Types
291
1212 range
293
1213 Floating Point Types
295
1214 Enumeration Types
297
1215 Physical Types
299
1216 Scalar Subtypes
301
1217 array Types
303
122 array Range
305
1221 array Subtypes and Aliasing
307
1222 array Slices
309
123 Strong Typing and Overloading
311
124 Arithmetic Operations
313
1241 exponentiation operation
315
1242 and Operators
317
1243 mod and rem
319
1244 Binary and Unary + and abs
321
125 subtype Calculations
323
126 Arithmetic Precedence
325
127 Exercises
326
Type Conversions Overloading and Resolution Functions
327
131 Converting Types
329
1311 Typemark Conversion
331
1312 Valid Typemark Conversions
333
1313 Usercreated Conversions
335
132 Overloading
337
1321 Enumeration Overloading
339
1322 Subprogram Overloading
341
1323 Overloaded Subprogram Calls
343
1324 Overloading Operators
345
1325 Overloaded Operator Calls
347
1326 Operator Overloading Rules
349
133 Multiple Signal Drivers
351
134 Resolution Functions
353
1341 Creating Resolution Functions
355
1342 Creating Resolved Signals
357
1343 Resolution Function Example
359
135 Exercises
360
Scope Visibility Packages and Libraries
361
141 Declarations
363
1411 Declarative Regions
365
142 Scope and Visibility
367
1421 Scope
369
1422 Visibility
371
143 Mutual Exclusion
373
144 Selected Names
375
145 Packages
377
1451 Package Declaration
379
1452 Package Body
381
1453 Setting up Packages
383
146 Deferred Constants
385
147 Using Packages
387
148 Predefined Packages
389
149 Libraries
391
1491 Working Library
393
1493 Accessing Libraries
395
1494 PackageLibrary Example
397
1410 Exercises
398
TEXTIO Blocks and Guards
399
151 Textual Input and Output
401
152 Package TEXTIO
403
153 Identifying Files
405
1531 ReadingWriting Files
407
1532 Processing Files
409
1533 File Example
411
154 Design Partition
413
155 Block Statement
415
1551 Using Blocks
417
1552 Example of Partitioning
419
1553 Guard Expression
421
1554 Guarded Assignment
423
1555 Guarded Signal Assignment
425
156 Block Declaratives
427
1561 Block Attributes
429
157 Exercises
430
Structural Modelling Generics and Generate
431
161 Structural Modelling
433
162 Component Declaration
435
1621 Component Instantiation
437
1622 Component Specification
439
163 Structural Layout
441
1631 Structural Example
443
1632 Structural Model
445
164 Generics
447
1641 Generic Statement
449
1642 Mapping Generic Values
451
1643 Generic Use Example
453
165 Configuration Declarations
455
166 Generate Statement
457
167 Generate Example
459
168 Exercises
460
Glossary of Terms
461
Language Construct Tree
467
Language Changes 1993
469
Index
477
Copyright

Other editions - View all

Introduction to VHDL: Solutions manual
R.D. Hunter
No preview available - 1997

Common terms and phrases

activity Algorithmic appear architecture body architecture example array type ASSERT statement associated attributes begin Binary operators BIT_VECTOR BOOLEAN called Chapter clause clock clocking signal compiled component declaration component instantiation concatenation concurrent signal assignment concurrent statements conditional signal assignment constant declarative area declarative region defined delay design entity elements end example end loop end process entity declaration enumeration type evaluated executed expression floating point hardware Hardware Description Languages identifier name IEEE Illumination Box integer iteration label left operand logical operators mode multiple nand_gate out_1 output signal overloaded package body package declaration parameter list port map predefined types process statement READLINE relational operators resolution function return statement return value right_operand scalar selected signal assignment sequential statements signal assignment statement simulation specification Std_logic structural model subprogram subtype TEXTIO truth table type BIT type declaration Typemark value set variable VHDL wait statement waveform xor_gate

References to this book

Bibliographic information

TitleIntroduction to VHDL
AuthorsR.D. Hunter, T. T. Johnson
Editionillustrated
PublisherSpringer Science & Business Media, 1996
ISBN0412731304, 9780412731303
Length482 pages
  
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